RTL Design

Experience Range: 5 to 15 years

Principal Accountabilities:

• Design of optimized digital blocks meeting functional, cost and low power constraints and ensure spec compliance.

• Develop TCL scripts and design constraints to perform synthesis, DFT insertion and static timing analysis.

• Support DFT strategy and implementation.

• Verification planning, feature extraction and verification test case development.

• Interface with P & R for digital hand-off and post layout verification.

• Develop test vectors for production test.

• Perform physical silicon device evaluation where necessary.

• Produce high quality documentation for own blocks.

• Develop work-around solutions where necessary to overcome device errata including documentation.

• All other tasks as deemed reasonable by your manager some of which will be set during annual performance review.

Key Performance Measures: (How will success in the job be measured? These should relate to the Principal Accountabilities.)

• Pro-actively taking ownership of responsibilities.

• Deliver work in the agreed timescales as set by program schedule for all assigned tasks.

• Accurate documentation and log all design work.

• Can exercise judgement within defined procedures to determine best action.

• Looks for continuous improvement in own and Renesas work practises.

• Apply policy/procedures to resolve routine issues.

• Self-motivated and service-minded.

• Awareness of “TAGIE” and follow principals throughout work.

• Demonstrates good team spirit both in own team and cross functional teams.

• Proactively seeks improvement in technical and non-technical skills and knowledge through self-development, course attendance and on the job training.

Qualifications:

• Experience in Logic design /micro-architecture / RTL coding.

• Must have hands on experience with Power product design, synthesis and timing analysis for complex Analog Circuits.

• Experience in Verilog/System-Verilog is a must.

• Experience working in semiconductor ideally PMIC or Audio with focus on mixed signal integrated circuits

• Hands on experience developing block and top-level timing constraints for STA and P & R sign off

• Knowledge of scan insertion and ATPG generation

• Understanding of design constraints and synthesis scripts

• Work independently on straightforward tasks, with little direction from manager

• Ability to propose innovative solutions

• Results-oriented and able to deliver on-time under a tight schedule

• Cross cultural awareness and sensitivity

• Proactive attitude about own role and contribution to company goals

• Ability to work both independently and part of a team

• Flexible to undertake occasional international travel at short notice

• Excellent command of verbal and written English

• Concise and precise communication and interpersonal skills within multi-site and multi-cultural environment